1) Field of the Invention
The present invention relates to a technology for evaluating a wiring condition among cells disposed in a specified region, which is developed to decide arrangement of cells (circuit elements) for designing an integrated circuit such as an LSI or circuitry on a printed circuit board. More particularly, the invention relates to a method for predicting a wiring density among cells, a storage medium for storing a wiring density predicting program and a cell arranging device for arranging cells by using the wiring density predicting method.
2) Description of the Related Art
Generally, for designing an integrated circuit such as an LSI, first, logical designing is performed based on logical specifications which satisfy functions of an LSI to be designed. Then, packaging designing is performed based on a net list obtained by the logical designing. During packaging designing, cells (circuit elements) are arranged based on the net list and then wiring is performed among the cells.
A conventional interactive cell arranging system has used a procedure like that shown in FIG. 16 for arranging cells while evaluating a wiring condition.
The specific procedure goes as follows. First, cells are properly disposed in a specified region based on a net list (step S1). Then, for evaluating a wiring condition among the cells disposed in the specified region, a certain wiring program is started to perform temporary wiring (global wiring or Manhattan wiring) among the cells (step S2). Then, based on the result of the temporary wiring, a wiring density among the cells is determined and a wiring condition is evaluated (step S3).
If the cell arrangement is determined to be O.K. as a result of evaluating the wiring condition (YES route from step S4), the process proceeds to an actual wiring operation (step S6). On the other hand, if the wiring condition is not good (NO route from step S4), the cells are rearranged (step S5). Then, the process returns to step S2 and repeats the operations from step S2 to step S5. In this way, the cells are arranged in a good wiring condition (i.e., a condition for enabling real wiring to be quickly performed) before a real wiring operation is performed.
However, there is a problem inherent in the foregoing conventional interactive cell arranging system. Specifically, as described above with reference to FIG. 16, for evaluating a wiring condition among the cells disposed in the specified region, temporary wiring is performed by running a wiring program for each of the results of arranging in step S1 and step S5 and a wiring density is then obtained. Consequently, a great deal of time is required for temporary wiring processing.
Generally, considerable time is needed for wiring processing among cells, even for such easily estimated wiring as Manhattan wiring or the like. Especially, as a circuit is larger in size, more time is needed. As a result, if a wiring program is run for each rearranging of cells, a great deal of time is required for realizing cell arrangement of a good wiring condition and even circuit designing efficiency is greatly reduced.